1. Field of the Invention
The present invention generally relates to a logic optimization device for automatically designing integrated circuits. More specifically, the present invention relates to a logic optimization device for deleting an unnecessary output port, thereby producing a consistent hierarchical gate-level net-list.
2. Description of Background Art
In a method for designing a hierarchical integrated circuit, a plurality of circuit-design descriptions representing a multi-layered blocks of the hierarchical integrated circuit are first prepared in RTL (register transfer level). Then, the plurality of RTL circuit-design descriptions are subject to a logic synthesis, and are assembled to a net-list in gate-level (logic circuit level).
In another method, a final gate-level net-list of a whole hierarchical integrated circuit including a multi-layered blocks is generated on the basis of a plurality of componential gate-level net-lists each of which represents a respective layer.
In such design methods, each circuit-design description or each componential net-list is frequently prepared such that the corresponding layer block includes superfluous elements in order that this layer can be utilized for plurality sorts of upper layer blocks. In this case, the lower layer block inevitably includes one or more elements that are not used for an individual upper layer block.
When a logic synthesis is executed on circuit-design descriptions of such a lower layer block having superfluous elements and a upper layer block, the final net-list of the whole integrated circuit also prescribes one or more redundant output terminals and logics that are not used for the upper layer block. Accordingly, there is likelihood that one or more unnecessary circuits are left in the final net-list. The same problem occurs when a final gate-level net-list of a whole hierarchical integrated circuit is assembled from a componential gate-level net-list describing a lower layer block including superfluous elements and another componential gate-level net-list describing an upper layer block.
Accordingly, some conventional logic optimization device can deletes redundant logics relevant to output terminals that are not connected to elements at their upper layer block when such output terminals are indicated by a human designer at the logic synthesis process.
However, with respect to such a conventional logic optimization device, the designer should know in advance the unnecessary output terminals that are not connected with elements in their upper layer block in order to exclude redundant elements.
Furthermore, when a plurality of the same lower layer blocks are connected with an upper layer block, but the lower layer blocks have different output terminals that are not connected with the upper layer block, the above-described method will be complicated.
Additionally, a similar problem arises if a constant or fixed input is given to an input terminal of a gate at a lower layer from an upper layer. In such a case, an architectural part including the gate at the lower layer and some element at the upper layer may be deleted or replaced with a simpler architectural part since a constant input is given to the input terminal of the gate. However, there has not been an idea for replacing or deleting such an architectural part over a plurality of layers, so that unnecessary elements are left in the final net-list.
It is therefore an object of the present invention to provide a logic optimization device for simplifying elements in multiple layers of a hierarchical integrated circuit automatically, thereby producing a wasteless hierarchical gate-level net-list.
In accordance with an aspect of the present invention, a logic optimization device includes a decider for referring to hierarchical circuit-design descriptions representing multiple layers of an integrated circuit, and for deciding whether or not each output terminal at each lower layer is connected with its upper layer. The logic optimization device also includes a modifier for deleting from the hierarchical circuit-design descriptions an information part describing an output terminal at a lower layer that has been decided to be unconnected with its upper layer by the decider, and for deleting from the hierarchical circuit-design descriptions an information part describing an element at the lower layer connected with the output terminal, thereby producing a gate-level net-list of an integrated circuit.
With such a structure, it is possible to delete unnecessary elements at each layer of a hierarchical integrated circuit automatically, thereby producing a wasteless hierarchical gate-level net-list.
In accordance with another aspect of the present invention, a logic optimization device includes a decider for referring to hierarchical circuit-design descriptions representing multiple layers of an integrated circuit, and deciding whether or not each gate at each lower layer receives a fixed input from its upper layer. The logic optimization device also includes a modifier for replacing in the hierarchical circuit-design descriptions information parts describing an original architectural part including elements at a lower layer including a gate that has been decided to receive a fixed input by the decider and elements at its upper layer connected to an input terminal of the gate by alternative information parts describing an equivalent architectural part that is simpler than the original architectural part, or for deleting from the hierarchical circuit-design descriptions information parts describing the original architectural part, thereby producing a gate-level net-list of an integrated circuit.
With such a structure, it is also possible to delete unnecessary elements at each layer of a hierarchical integrated circuit automatically, thereby producing a wasteless hierarchical gate-level net-list.